1. Field of the Invention
The present invention relates to programmable memory cells, More particularly, the present invention relates to programmable memory cells utilized in a programmable logic device (PLD).
2. Description of the Related Art
FIG. 1 shows a circuit diagram for a conventional programmable memory cell utilized in PLDs. The memory cell of FIG. 1 includes an NMOS transistor 100 having a floating gate enabling the memory cell to be programmable. The source of NMOS transistor 100 is shown connected to a product term ground (PTG) node. The PTG node provides a connection to a similar PTG input of a sense amplifier in a PLD. The dashed line in transistor 100 indicates that additional arsenic ion implantation is utilized in its channel to reduce its threshold to approximately zero volts so that no voltage drop occurs from the source to drain of transistor 100. Without the additional arsenic ion implantation, transistor 100 would have an NMOS threshold which is significantly higher than zero volts.
The drain of transistor 100 is connected to a product term (PT) node through the source to drain path of NMOS pass transistor 108. The PT node provides a connection to a similar PT input of a sense amplifier in a PLD. A word line (WL) node voltage input is supplied to the gate of pass transistor 108 to enable or disable a path from the PT node to the source of transistor 100.
Capacitors 102 and 104 are utilized to add charge to and subtract charge from the floating gate of transistor 100. Capacitor 102 couples an array control gate (ACG) node voltage to the floating gate of transistor 100. Capacitor 104 is a tunneling capacitor which includes a thin tunneling oxide region. Charge is added to the floating gate during programming and removed from the floating gate during erase through the tunneling oxide region.
An NMOS pass gate transistor 106 has a drain connected to a second terminal of tunneling capacitor 104 to control voltage supplied to capacitor 104. The source of transistor 106 is connected to a word control (WC) node, while its gate is connected to the WL node similar to pass transistor 108.
FIG. 2 shows a cross sectional view of a layout of the NMOS pass transistor 106. As shown, the pass transistor 106 includes n-type source and drain implant regions 202 and 204 provided in a p-type substrate. To isolate the source and drain regions 202 and 204 of transistor 106 from other transistors, field oxide regions 206 and 208 are further implanted in the substrate. To prevent depletion of the channel between the source and drain regions 202 and 204 when an unusually high drain voltage is applied, a punch through implant region 210 is provided in the channel. Further, to provide the NMOS threshold typically found in NMOS transistors, a vt implant region 212 is also provided in the channel between regions 202 and 204.
To further identify the implants utilized in transistor 106, FIG. 3 plots dopant concentration vs. distance from the substrate surface for the punch through, vt, and field implants. As shown in FIG. 3, the implantation energy level of the punch through and vt implants, which is indicated by the distance from the surface of a majority of the dopant concentration, can be less than the implantation energy level for the field implant. Further, as shown, the energy level of the punch through implant is greater than the vt implant.
The appropriate voltages necessary for programming, or adding charge to the floating gate of transistor 100 in FIG. 1 are listed in Table I below.
TABLE I ______________________________________ WC WL ACG PT PTG ______________________________________ Program Vpp Vpp+ 0 Hiz 0 ______________________________________
The voltage Vpp indicates a pumped programming voltage which is on the order of 12 volts. As illustrated in FIG. 4, Vpp is provided by voltage pump circuitry 400 on a chip which increases a Vcc voltage supplied externally to the chip. Vcc is on the order of 5 volts. The voltage Vpp+ indicates the programming voltage plus an NMOS threshold, vtn, the total voltage Vpp+ typically being approximately 13.8 volts. As shown in FIG. 4, Vpp+ is provided by an additional voltage pump circuit 402.
During program, the additional NMOS threshold, vtn, above Vpp is required on the WL node to assure transistor 106 turns on. The additional voltage vtn above Vpp is provided by circuitry in voltage pump 402 in addition to the circuitry of voltage pump 400. Because the added voltage pump circuitry in voltage pump 402 typically provides an output through an NMOS transistor, the added circuitry pumps the voltage two times vtn above Vpp to obtain a WL voltage of Vpp+ which is one vtn above Vpp. Typical voltage pump circuitry is described in U.S. Pat. No. 5,263,000 entitled "Drain Power Supply", which is incorporated herein by reference.